RISC-V Capture The Bug

A Processor Design Verification Hackathon
Using Vyoma's UpTickPro tool



Online and Cloud based


15th July to 31st July, 2023

Registration starts from 5th July, 2023

About RISC-V Capture The Bug Hackathon

To introduce participants to the RISC-V ecosystem and familiarize them with the fundamentals of processor verification. Through this event, the RISC-V CTB imparts knowledge about the process of identifying bugs in RISC-V designs, emphasizing the importance of thorough processor verification.

The Indian Govt. Agency, the Ministry of Electronics and Information Technology, (MeitY) through its Digital India RISC-V (DIR-V) efforts in collaboration with RISC-V International and the Mentoring Academic, Institute Indian Institute of Technology Madras (IIT-Madras) , is committed towards skill development in the field of semiconductor domain with the focus of building next generation RISC-V processors. The hackathon aims to build expertise in design verification which enables a larger engineering community working towards better RISC-V quality. The hackathon helps build a RISC-V Processor Verification Community with the same collaborative spirit of the RISC-V International.

The RISC-V CTB 2023 hackathon is technically facilitated by Vyoma Systems, a DIR-V startup incubated at IITM Pravartak Technologies Foundation (IITM-PTF) which is working towards building skilled manpower in the domain of Processor Design Verification, which will strengthen the quality as well as the time to market requirements of the RISC-V designs being manufactured.

Who can participate?

  • Only individual participants (no group)
  • FREE Registration & Participation
  • Basic Computer Architecture Knowledge expected
  • Open to all verification enthusiasts, students and working professionals

Hackathon Schedule

Participants Registration Link

Hackathon Inauguration Webinar

Vyoma will introduce participants to the design verification challenge

RISC-V Processor Verification Initial Report

To ensure the understanding of the history of processor hardware bugs, please read about processor hardware bugs and choosing an open-source RISC-V processor design

Report Submission

Participants need to submit a 1 page report on processor hardware bugs and causes along with briefing about the chosen open-source RISC-V processor design. Individuals who do not submit the survey will not be able to advance to the capture the bug.

RISC-V Capture the bug

Participants who have submitted their 1 page documentation will receive 60 HOURS of access to the CTB Hackathon Challenge platform (along with video tutorials) to detect the bugs

Report Submission and documentation

Participants need to upload the verification environment that finds the bugs and also document the debugging information

CTB Results & Closing Webinar

Result Declaration and Announcements

CTB Results

Great Work CTB Champions!

Sean Dalton

Smart Mechatronics GmbH, Germany

Suresh Kumar Karthikeyan

Indian Institute of Technology Madras, India

Manish Patla

PES University, India

Gabriel Villanova Novaes Magalhães

VIRTUS, Brazil

Meet Sangani

Dharmsinh Desai University, India

Angela Gonzalez Marino

PlanV, Spain

Hassan Raza

10X-Engineers, Pakistan

Prashant Mata

Alphawave Semi, India

Prashant Laddha

Scaledge, India

Paulson K Antony

Robert Bosch, India

Jishnu Das

IIT-BHU, Varanasi, India

Callan Lee Hill


Kuhuk Narain

Siemens EDA, India

Shashank V M

Qualcomm, India

Megna Premkumar

Indian Institute of Technology, Madras, India

Sanjay Menon

Valtrix Systems, India

Surya Prasad S

IIT Madras, India

Shweta Kiran Totla

IIT Dharwad, India

Matthias Brugger


Luke Brazier

United Kingdom

Jayasri Palanisamy

PSG Institute of Technology and Applied Research, India

Nishant Sachdeva


Vinit Kumar

B S Abdur Rahman Crescent Institute of Science and Technology, India

Nonthaphat Jitchiranant

King Mongkut's Institute of Technology Ladkrabang, Thailand

Archita Amol Malgaonkar

Indian Institute of Technology Hyderabad, India

Sudeep Arunkumar Joshi

RV College of Engineering, India

Yellur Vishal Rao

Manipal Institute of Technology, India

Jatin Khanna

Amrita Vishwa Vidyapeet, India

Abhinav Prakash

IIT Hyderabad, India

Sanjay Sattva K

Indian Institute of Technology Madras, India

Garv Jain

Indian Institute of Technology, Patna, India

Bantita Wongwan

King Mongkut's Institute of Technology Ladkrabang, Thailand

Karthik Narayan C

Amrita Vishwa Vidyapeetham, India

Pitpibul Phongphotjanatham

King Mongkut's Institute of Technology Ladkrabang, Thailand

Sreevishnu S

Government Engineering College, Thrissur, India

Kartheeswaran Murugesan

Carleton University, Canada

Pavan Prakash Myagerimath

KLE Technological University, India

Mirza Amir Baig

Siemens EDA, India

Saketh Gajawada

International Institute Of Information Technology Bangalore, India

Devparno Ghosal

Techno Main Salt Lake, India

Vincent Alleaume


Jay Manthapurwar


Cathrene Biju

Cochin University of Science and Technology, India

Abel Joseph John

Digital University Kerala, India

Işıl Öz

Izmir Institute of Technology, Turkey

Anis Yagoub

Enseirb-MATMECA, France

sanjeev kumar

Micron Technology, India

Inderjit Singh Dhanjal

K.J Somaiya College of Engineering, India

Himanshu Kumar Rai

IIITB, India

Gaurav Tale

Shri Guru Gobind Singhji institute of Engineering and Technology, India


  • RISC-V History
  • ISA Specifications (Ratified) Volume 1, Unprivileged Specification version 20191213 [PDF]
  • ISA Specifications (Ratified) Volume 2, Privileged Specification version 20211203 [PDF]
  • RISC-V Assembly

System Requirements

The minimum requirements for running the tool are the following
  • Any OS
  • Firefox/Chrome Browser has been tested
  • Min 4 Mbps internet connection
  • Minimum of 2GB RAM on Laptop/PC
  • GitHub

Platform Used

  • Vyoma’s UpTickPro Platform caters to the next generation semiconductor needs for rapid RISC-V test development, test generation and processor design verification spanning various verification complexities
  • It is a verification-as-a-service platform that leverages state-of-the-art cloud compute and verification methodology
  • Straightforward to use to quickly develop your RISC-V tests for processor design verification.

Hackathon Challenge Statement

To use the RISC-V CTB Hackathon Platform provided and expose all the bugs in the tests, test generation and processor designs. It involves writing test scenarios in RISC-V Assembly to capture the bugs in the given designs. The hackathon platform access is for non-continuous 60 HOURS to complete the challenge.

Terms & Conditions

  • The hackathon challenges and test simulation has to be done only using Vyoma’s UpTickPro Platform
  • The tests are to be submitted in the platform itself and the submission guidelines have to be followed
  • This hackathon is open only to individuals. We will not accept team or group registration/submissions
  • Any participant found to be indulging in any form of malpractice will be immediately disqualified
  • The decision of the review committee and the organizers in declaring the results will be final. No queries in this regard will be entertained



  • Yes, participation is free for all. We would like to have the active involvement of students and professionals in the VLSI verification domain and hence the motivation. You are, however, required to provide your correct information for identification purposes during the registration process.

  • On completion of registration, participants will be given an overview of processor design bugs. The screening process requires the participants to choose an open source RISC-V Processor Design of their own, understand its implementation and submit a report detailing the design and verification strategy. Only participants successfully completing the report will be provided with the Design Verification Challenges.

  • On completion of registration, participants will be given an overview of RISC-V, its verification tutorials and the setup required for the hackathon. As part of the hackathon, you will be required to develop or fix the buggy RISC-V test cases in the setup provided to identify bugs at 3 complexity levels. More information and support will be provided as part of the hackathon.

    • RISC-V CTB Hackathon Level 1: Compilation and Model Bugs
    • RISC-V CTB Hackathon Level 2: Test Generation Bugs
    • RISC-V CTB Hackathon Level 3: RISC-V Processor Design Bugs
  • Yes, absolutely! The hackathon is developed in such a way that very minimal basics of RISC-V and Verilog are required. Design or verification knowledge would be helpful. However, all that is required is the attitude to want to learn independently, try out new challenges and have fun in the process.

    • Get a basic understanding of the semiconductor industry and verification flow.
    • Get a hands-on experience on the RISC-V activities. Have an understanding of design verification as a career path.
    • Get an e-certificate on successful completion of screening as well as the CTB verification challenges.



Technical Facilitator